The fabrication of integrated chips can be broadly broken into two main sections, a front-end-of-the-line and a back-end-of-the-line. Front-end-of-the-line fabrication includes the formation of devices (e.g., transistors, capacitors, resistors, etc.) within a semiconductor substrate. Back-end-of-the-line fabrication includes the formation of metal interconnect layers comprised within insulating dielectric material disposed above the semiconductor substrate. The metal interconnect layers electrically connect individual devices of the front-end-of-the-line to external pins of an integrated chip.
Front-end-of-the-line devices are typically connected to back-end-of-the-line metal interconnect layers by way of a contact (i.e., a via) that extends vertically between one or more areas of a device and a first metal interconnect layer. For example, MOS field effect transistors may comprise a source, drain, and gate that are connected to a back-end-of-the-line metal interconnect layer by way of separate contacts.